The present invention relates to integrated circuits and, more particularly, to integrated circuit memory devices. A major objective of the present invention is to provide for erasable programmable logic devices (EPLDs) that achieve high operating speeds with relatively low power requirements.
Much of modern progress is associated with the increasing functionality and speed of integrated circuits. When produced in large quantities, integrated circuits are sufficiently inexpensive that computers, instruments, and consumer products incorporating them are within the reach of everyone. However, very high start-up costs, including research, manufacturing facilities, design, processing, and testing, can be prohibitive for small volume applications. Low volume runs are important, not only for certain specialized applications, but as intermediate steps in the development of integrated circuits eventually destined for large volume production.
Various "application-specific integrated circuit" (ASIC) technologies have addressed the problem of start-up costs. However, because they involve reliance on further manufacturing to realize a design, start-up costs are higher than desired for many applications.
Where the desired functionality can be achieved, programmable devices afford a very attractive approach to small volume integrated circuit manufacturing. The functionality of programmable devices is determined after they are manufactured, typically by selecting binary values to be stored in included memory cells. The most basic programmable device is a programmable read-only memory (PROM). Programming a PROM determines what data will be output for each of its memory addresses.
Programmable device designs can be updated or improved and then implemented by a device replacement. Erasable programmable devices permit updates by erasing the old and programming the new without changing the integrated circuit. While many erasable devices rely on exposure to ultra-violet radiation for erasure, others, notably electrically-erasable programmable read-only memories (EEPROMS) and their logic counterparts can be erased in circuit. The advantages of erasable devices, especially those that are electrically erasable, during iterative design stages is clear. Their susceptibility to improvements has made such devices attractive even in high volume applications.
More sophisticated functionality can be achieved using programmable logic arrays (PLAs), which allow post-manufacturing selection of logic functions by storing binary values in included memory cells. The erasable counterpart to the PLA is the erasable programmable logic device EPLD, which offers both sophisticated functionality and the convenience of reprogrammability.
Logical functions can be expressed as a combination of inversions, AND functions (logical products), and OR functions (logical sums). A typical functional block of an EPLD includes a bank of OR gates, each of which is fed by several AND gates, each of which is fed by both inverted and uninverted inputs. The output of such a logical block is the logical sum of logical products of inverted and uninverted inputs. Any logical product including both a binary value and its inverse is zero, so provision is made for deactivating one of each complementary pair of the inputs to permit nonzero outputs.
More specifically, each AND gate in such an EPLD function block has an associated bit line. EPROM elements are connected in parallel between each bit line and a "virtual ground" line, which is maintained at a relatively low voltage. When any of its EPROM elements are conductive, a bit line assumes a logic low voltage. Otherwise, it assumes a logic high voltage. When an EPROM element is unprogrammed, a logic high voltage applied to its gate (control) input renders it conductive; while a logic low gate input voltage renders it nonconductive. When the EPROM element is programmed, it is nonconductive irrespective of the gate voltage. Thus, the control inputs of only the unprogrammed (erased) EPROM elements function as AND gate inputs.
Typically, the EPROM elements are arranged in a two-dimensional array. The control inputs of EPROMs in a row are connected to a common word line. EPROMs in a column are connected to a common bit line. The word lines are arranged in inverted/uninverted pairs to provide inverted inputs as necessitated by the overall logic function to be implemented. EPROM elements that are not required are programmed to be nonconductive. The EPROMs do not consume power when nonconducting; in the context of an AND array, programmed EPROMs remain in a "high" state, which is the innocuous state for an AND gate input. A typical application would require most of the EPROM elements to be programmed, which can be a relatively time-consuming process.
Each bit line of the AND array is coupled to the input of a sense amplifier, which serves to amplify and buffer the voltage representing the AND gate output on its way to an input of an OR gate to contribute to the final sum of products logical output. The sense amplifier can have the same or the opposite sense as the bit line. Given a sense amplifier output with the same sense as the connected bit line, when all of the associated EPROM elements are nonconductive, the bit line and the sense amplifier output are high. When any of the associated EPROM elements are conductive, the bit line and the sense amplifier output transition to a low output. When next all associated EPROMs are nonconductive, the bit line and the sense amplifier output transition to a high output.
The transition from low to high is not instantaneous. Capacitances, including those associated with each of the connected EPROM elements, must be filled before the logic high voltage is reached. The rate at which the capacitances are filled depends on the magnitude of the source current. A larger source current provides for a faster low-to-high bit-line transition. The faster this transition is completed, more promptly the AND array can respond reliably to a new input. The faster new inputs can be handled, the higher the performance of the overall EPLD device. Since the market's appetite for higher performance appears insatiable, faster is better all else being equal.
Unfortunately, not all else is equal since a larger source current involves greater power consumption. Greater power consumption can mean greater electrical costs; for battery powered devices, it can mean shorter battery lifetimes greater power consumption also results in greater heat dissipation, which is a major factor in device failures. If the greater heat dissipation is compensated for by peripheral cooling systems, this adds cost and complexity to the system.
Accordingly, EPLD designers (as well as designers of other memory and logic devices) are confronted with a conflict between the objectives of greater speed and lower power consumption. What is needed is an approach to achieving higher performance with less of a penalty in power consumption.